CMOS switch circuits having complementary outputs are useful in circuit applications such as driving the control inputs of a transmission gate. In such and other applications, it is desirable for the complementary outputs to switch concurrently to minimize noise injection into the circuit.
In a conventional method of designing a CMOS switch circuit, the circuit is optimized for concurrent switching during computer simulation employing timing models associated with nominal process parameters. In practice, however, process variations during manufacture are inevitable. Accordingly, switching of the complementary outputs of such manufactured CMOS switch circuits may be less than concurrent.